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CY8C27143, CY8C27243 CY8C27443, CY8C27543 CY8C27643
PSoC(R) Programmable System-on-ChipTM
PSoC(R) Programmable System-on-Chip
Features
Powerful Harvard-architecture processor M8C processor speeds up to 24 MHz 8 x 8 multiply, 32-bit accumulate Low power at high speed Operating voltage: 3.0 V to 5.25 V Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) Industrial temperature range: -40 C to +85 C Advanced peripherals (PSoC(R) blocks) Tweleve rail-to-rail analog PSoC blocks provide: * Up to 14-bit analog-to-digital converters (ADCs) * Up to 9-bit digital-to-analog converters (DACs) * Programmable gain amplifiers (PGAs) * Programmable filters and comparators Eight digital PSoC blocks provide: * 8- to 32-bit timers, counters, and pulse width modulators (PWMs) * Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules * Up to two full-duplex universal asynchronous receiver transmitters (UARTs) * Multiple serial peripheral interface (SPI)masters or slaves * Connectable to all general-purpose I/O (GPIO) pins Complex peripherals by combining blocks Precision, programmable clocking Internal 2.5% 24- / 48-MHz main oscillator 24- / 48-MHz with optional 32 kHz crystal Optional external oscillator up to 24 MHz Internal oscillator for watchdog and sleep Flexible on-chip memory 16 KB flash program storage 50,000 erase/write cycles 256-bytes SRAM data storage In-system serial programming (ISSP) Partial flash updates Flexible protection modes Electronically erasable programmable read only memory (EEPROM) emulation in flash Programmable pin configurations 25-mA sink, 10-mA source on all GPIOs Pull-up, pull-down, high-Z, strong, or open-drain drive modes on all GPIOs Eight standard analog inputs on GPIO, plus four additional analog inputs with restricted routing Four 30-mA analog outputs on GPIOs Configurable interrupt on all GPIOs
Additional system resources 2 I C slave, master, and multi-master to 400 kHz Watchdog and sleep timers User-configurable low-voltage detection (LVD) Integrated supervisory circuit On-chip precision voltage reference Complete development tools Free development software (PSoC DesignerTM) Full-featured, in-circuit emulator (ICE) and programmer Full-speed emulation Complex breakpoint structure 128 KB trace memory
Logic Block Diagram
PSoC CORE
System Bus
Global Digital Interconnect SRAM 256 Bytes Interrupt Controller
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers
Global Analog Interconnect Flash 16 KB Sleep and Watchdog
SROM
CPU Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
Analog Input Muxing
Digital Clocks
Multiply Accum.
POR and LVD Decimator I2 C System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 38-12012 Rev. *T
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 23, 2011
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Contents
PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ............................................................. 3 Analog System ............................................................ 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 7 PSoC Designer Software Subsystems ........................ 7 Designing with PSoC Designer ....................................... 8 Select User Modules ................................................... 8 Configure User Modules .............................................. 8 Organize and Connect ................................................ 8 Generate, Verify, and Debug ....................................... 8 Pinouts .............................................................................. 9 8-pin Part Pinout ......................................................... 9 20-pin Part Pinout ....................................................... 9 28-pin Part Pinout ..................................................... 10 44-pin Part Pinout ..................................................... 11 48-pin Part Pinout ...................................................... 12 56-pin Part Pinout ...................................................... 14 Register Reference ......................................................... 16 Register Conventions ................................................ 16 Register Mapping Tables .......................................... 16 Electrical Specifications ................................................ 19 Absolute Maximum Ratings ....................................... 19 Operating Temperature ............................................. 20 DC Electrical Characteristics ..................................... 20 AC Electrical Characteristics ..................................... 35 Packaging Information ................................................... 44 Packaging Dimensions .............................................. 44 Thermal Impedances ................................................ 50 Capacitance on Crystal Pins .................................... 50 Solder Reflow Peak Temperature ............................. 50 Development Tool Selection ......................................... 51 Software .................................................................... 51 Development Kits ...................................................... 51 Evaluation Tools ........................................................ 51 Device Programmers ................................................. 52 Accessories (Emulation and Programming) ................ 52 Ordering Information ...................................................... 53 Ordering Code Definitions ........................................ 54 Acronyms ........................................................................ 55 Reference Documents .................................................... 55 Document Conventions ................................................. 56 Units of Measure ....................................................... 56 Numeric Conventions ................................................ 56 Glossary .......................................................................... 56 Document History Page ................................................ 61 Sales, Solutions, and Legal Information ...................... 63 Worldwide Sales and Design Support ....................... 63 Products .................................................................... 63 PSoC Solutions ......................................................... 63
Document Number: 38-12012 Rev. *T
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PSoC Functional Overview
The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture lets you to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated in Logic Block Diagram on page 1, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C27x43 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to eight digital blocks and 12 analog blocks.
Digital System
The digital system is composed of eight digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Figure 1. Digital System Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Digital Clocks FromCore
To System Bus
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
Row Output Configuration
PSoC Core
The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included sleep and watchdog timers (WDT). Memory encompasses 16 KB of flash for program storage, 256 bytes of SRAM for data storage, and up to 2 K of EEPROM emulated using the flash. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24-MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. The 24-MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32-kHz internal low speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is desired, the 32.768-kHz external crystal oscillator (ECO) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24-MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
8 8
8
Row Input Configuration
Row 1
DBB10 DBB11 DCB12
4 DCB13 4
8 Row Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include:

PWMs (8- to 32-bit) PWMs with dead band (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) UART 8-bit with selectable parity (up to two) SPI slave and master (up to two) I2C slave and multi-master (one available as a system resource) CRC/generator (8- to 32-bit) IrDA (up to two) Pseudo random sequence (PRS) generators (8- to 32-bit)
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The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This lets you the optimum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Characteristics on page 5. Analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks, as shown in the following figure. Figure 2. Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Analog System
The analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are as follows:

P2[3]
P2[4] P2[2] P2[0]
P2[1]
ADCs (up to 4, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and SAR) Filters (2, 4, 6, and 8 pole band pass, low pass, and notch) Amplifiers (up to four, with selectable gain to 48x) Instrumentation amplifiers (up to two, with selectable gain to 93x) Comparators (up to four, with 16 selectable thresholds) DACs (up to four, with 6- to 9-bit resolution) Multiplying DACs (up to four, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a core resource) 1.3-V reference (as a system resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible
M8C Interface (Address Bus, Data Bus, Etc.) Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap ACB00 ASC10 ASD20
ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0]
Array Input Configuration
Block Array
ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog Reference
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Additional System Resources
System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset.

The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. LVD interrupts can signal the application of falling voltage levels, while the advanced power-on reset (POR) circuit eliminates the need for a system supervisor. An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2-V battery cell, providing a low cost boost converter.
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs.

PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this datasheet is highlighted in Table 1. Table 1. PSoC Device Characteristics
PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x23 CY8C20x34 CY8C20xx6 Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[1] 12 6 6 4 6[1] 6
[1]
SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2 K
Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K
4[1] 4[1] 3[1, 2] 3[1, 2]
Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense(R).
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Getting Started
For in depth information, along with detailed programming details, see the PSoC(R) Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web.
Solutions Library
Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
Application Notes
Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs.
Technical Support
Technical support - including a searchable Knowledge Base articles and technical forums - is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736.
Development Kits
PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the CYPros Consultants web site.
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Development Tools
PSoC DesignerTM is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes:

Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation.
Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation
Built-in support for communication interfaces: 2 Hardware and software I C slaves and masters Full-speed USB 2.0 Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application.
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Designing with PSoC Designer
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug.
Organize and Connect
You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called "user modules." User modules make selecting and implementing peripheral devices, both analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design.
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Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital I/O. However, Vss, VDD, SMP, and XRES are not capable of Digital I/O.
8-pin Part Pinout
Table 2. Pin Definitions - 8-pin PDIP
Pin No. 1 2 3 4 5 6 7 8 I/O I/O I/O Power I/O I/O Type Digital I/O I/O I/O Power Analog I/O I/O Pin Name P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Description Analog column mux input and column output Analog column mux input and column output Crystal Input (XTALin), I2C serial clock (SCL), ISSP-SCLK[3] Ground connection. Crystal output (XTALout), I2C serial data (SDA), ISSP-SDATA[3] Analog column mux input and column output Analog column mux input and column output Supply voltage
Figure 3. CY8C27143 8-pin PSoC Device
A, IO, P0[5] A, IO, P0[3] I2CSCL, XTALin, P1[1] VSS
1 8 VDD 2 PDIP 7 P0[4], A, IO 3 6 P0[2], A, IO 4 5 P1[0], XTALout, I2CSDA
VDD
LEGEND: A = Analog, I = Input, and O = Output.
20-pin Part Pinout
Table 3. Pin Definitions - 20-pin SSOP, SOIC
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O I/O I/O I/O Power I/O I/O I/O I/O Input I I/O I/O I I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O Power Analog I I/O I/O I Pin Name P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] VDD Active high external reset with internal pull down Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Optional external clock input (EXTCLK) Crystal input (XTALin), I2C SCL, ISSP-SCLK[3] Ground connection. Crystal output (XTALout), I2C SDA, ISSP-SDATA[3] Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Switch Mode Pump (SMP) connection to external components required I2C Serial Clock (SCL) I2C Serial Data (SDA)
Figure 4. CY8C27243 20-pin PSoC Device
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] SMP I2CSCL, P1[7] I2CSDA, P1[5] P1[3] I2CSCL, XTALin, P1[1] VSS
1 2 3 4 5 6 7 8 9 10
SSOP SOIC
20 19 18 17 16 15 14 13 12 11
VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
LEGEND: A = Analog, I = Input, and O = Output.
Note 3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
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28-pin Part Pinout
Table 4. Pin Definitions - 28-pin PDIP, SSOP, SOIC
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I/O I/O I/O I/O Input I I I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I I Analog I I/O I/O I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Active high external reset with internal pull down Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Optional external clock input (EXTCLK) Crystal input (XTALin), I2C SCL, ISSP-SCLK[4] Ground connection. Crystal output (XTALout), I2C SDA, ISSP-SDATA[4] Direct switched capacitor block input Direct switched capacitor block input Switch mode pump (SMP) connection to external components required I2C SCL I2C SDA Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS
Figure 5. CY8C27443 28-pin PSoC Device
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PDIP SSOP SOIC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2CSDA
LEGEND: A = Analog, I = Input, and O = Output.
Note 4. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
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44-pin Part Pinout
Table 5. Pin Definitions - 44-pin TQFP
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Type Digital Analog I/O I/O I I/O I I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O Power I/O Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] Description Direct switched capacitor block input Direct switched capacitor block input
Figure 6. CY8C27543 44-pin PSoC Device
SMP connection to external components required
I2C SCL I2C SDA Crystal input (XTALin), I2C SCL, ISSP-SCLK[5] Ground connection. Crystal output (XTALout), I2C SDA, ISSP-SDATA[5]
19 I/O P1[2] 20 I/O P1[4] Optional external clock input (EXTCLK) 21 I/O P1[6] 22 I/O P3[0] 23 I/O P3[2] 24 I/O P3[4] 25 I/O P3[6] 26 Input XRES Active high external reset with internal pull down 27 I/O P4[0] 28 I/O P4[2] 29 I/O P4[4] 30 I/O P4[6] 31 I/O I P2[0] Direct switched capacitor block input 32 I/O I P2[2] Direct switched capacitor block input 33 I/O P2[4] External Analog Ground (AGND) 34 I/O P2[6] External Voltage Reference (VRef) 35 I/O I P0[0] Analog column mux input 36 I/O I/O P0[2] Analog column mux input and column output 37 I/O I/O P0[4] Analog column mux input and column output 38 I/O I P0[6] Analog column mux input 39 Power VDD Supply voltage 40 I/O I P0[7] Analog column mux input 41 I/O I/O P0[5] Analog column mux input and column output 42 I/O I/O P0[3] Analog column mux input and column output 43 I/O I P0[1] Analog column mux input 44 I/O P2[7] LEGEND: A = Analog, I = Input, and O = Output.
Note 5. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *T
P3[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P3[0]
12 13 14 15 16 17 18 19 20 21 22
P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3]
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef
TQFP
P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2]
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48-pin Part Pinout
Table 6. Pin Definitions - 48-pin Part Pinout (SSOP)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power
Type Pin Digital Analog Name
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I/O I/O I P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD I2C SCL I2C SDA
Description
Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input
Figure 7. CY8C27643 48-pin PSoC Device
Direct switched capacitor block input Direct switched capacitor block input
SMP connection to external components required
Crystal Input (XTALin), I2C SCL, ISSP-SCLK[6] Ground connection Crystal output (XTALout), I2C SDA, ISSP-SDATA.[6] Optional external clock input (EXTCLK)
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
Active high external reset with internal pull down
Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VRef) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Note 6. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *T
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Table 7. Pin Definitions - 48-pin Part Pinout (QFN)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O Power Analog I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Active high external reset with internal pull down Optional external clock input (EXTCLK) Crystal input (XTALin), I2C SCL, ISSP-SCLK[8] Ground connection. Crystal output (XTALout), I2C SDA, ISSP-SDATA[8] I2C SCL I2C SDA SMP connection to external components required Description Direct switched capacitor block input Direct switched capacitor block input
Figure 8. CY8C27643 48-pin PSoC Device[7]
VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0]
VDD
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Notes 7. The QFN package has a center pad that must be connected to ground (Vss). 8. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12012 Rev. *T
P5[1] 13 I2C SCL, P1[7] 14 I2C SDA, P1[5] 15 P1[3] 16 I2C SCL, XTALin, P1[1] 17 VSS 18 I2C SDA, XTALout, P1[0] 19 P1[2] 20 EXTCLK, P1[4] 21 P1[6] 22 P5[0] 23 P5[2] 24
A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3]
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37
P2[5] P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I
QFN
(Top View)
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56-pin Part Pinout
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8. Pin Definitions - 56-pin Part Pinout (SSOP)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type Digital Analog I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OCD OCD Power I/O I/O I/O I/O I I I I Pin Name NC P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP P3[7] P3[5] P3[3] P3[1] Description No connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input
Figure 9. CY8C27002 56-pin PSoC Device
NC AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] NC P1[3] SCLK, I2C SCL, XTALIn, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] CCLK HCLK XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALOut, I2C SDA, S NC NC
I I
Direct switched capacitor block input Direct switched capacitor block input
SSOP
I I
OCD even data I/O OCD odd data output SMP connection to required external components
Not for Production
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
I/O I/O I/O I/O I/O I/O Power
P5[3] P5[1] P1[7] P1[5] NC P1[3] P1[1] VDD NC NC P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] I2C SCL I2C SDA No connection Crystal Input (XTALin), I2C SCL, ISSP-SCLK[9] Supply voltage No connection No connection Crystal output (XTALout), I2C SDA, ISSP-SDATA[9] Optional external clock input (EXTCLK)
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Note 9. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *T
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Table 8. Pin Definitions - 56-pin Part Pinout (SSOP) (continued)
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Type Digital Analog OCD OCD I/O I/O I/O I/O I/O I I/O I I/O I/O I/O I I/O I I/O I/O Power I I Pin Name HCLK CCLK P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description OCD high-speed clock output OCD CPU clock output
Direct switched capacitor block input Direct switched capacitor block input External Analog Ground (AGND) External Voltage Reference (VRef) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Document Number: 38-12012 Rev. *T
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Register Reference
This section lists the registers of the CY8C27x43 PSoC device. For detailed register information, see the PSoC Programmable System-on-Chip Technical Reference Manual.
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set, the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed.
Register Conventions
The register conventions specific to this section are listed in the following table. Table 9. Register Conventions
Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
Table 10. Register Map Bank 0 Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Name Name Name
00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B 1C 1D 1E 1F DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 Blank fields are Reserved and must not be accessed.
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 RW
RW # # RW
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 # Access is bit specific.
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6
RW # RW # RW RW RW RW RW RW RC W RC RC RW
Document Number: 38-12012 Rev. *T
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Table 10. Register Map Bank 0 Table: User Space (continued)
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Name Name Name Name
DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # DCB03DR1 2D W DCB03DR2 2E RW DCB03CR0 2F # DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and must not be accessed.
67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW
CPU_SCR1 CPU_SCR0
E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW W W R R RW RW RW RW
RL
# #
Table 11. Register Map Bank 1 Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name
00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B 1C Blank fields are Reserved and must not be accessed.
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C
ASC10CR0 80 ASC10CR1 81 ASC10CR2 82 ASC10CR3 83 ASD11CR0 84 ASD11CR1 85 ASD11CR2 86 ASD11CR3 87 ASC12CR0 88 ASC12CR1 89 ASC12CR2 8A ASC12CR3 8B ASD13CR0 8C ASD13CR1 8D ASD13CR2 8E ASD13CR3 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 ASD22CR0 98 ASD22CR1 99 ASD22CR2 9A ASD22CR3 9B ASC23CR0 9C # Access is bit specific.
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC
RW RW RW RW
Document Number: 38-12012 Rev. *T
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Table 11. Register Map Bank 1 Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
1D 1E 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW DCB03IN 2D RW DCB03OU 2E RW 2F DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and must not be accessed.
5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
RW RW RW RW
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific.
ASC23CR1 ASC23CR2 ASC23CR3
RW RW RW
OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR
RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW
CPU_SCR1 CPU_SCR0
DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW RW RW RW RW RW RW R
W W RW W
RL
# #
Document Number: 38-12012 Rev. *T
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Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com. Specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40 C TA 70 C and TJ 82 C. Figure 10. Voltage versus CPU Frequency
5.25
4.75 Vdd Voltage 3.00 93 kHz
CPU Fre que ncy
O
l id g Va atin n r pe gio Re
12 MHz 24 MHz
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings
Symbol TSTG Description Storage temperature Min -55 Typ 25 Max +100 Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 C 25 C. Extended duration storage temperatures above 65 C degrade reliability.
C
TBAKETEMP tBAKETIME TA VDD VIO VIOZ IMIO IMAIO ESD LU
Bake temperature Bake time Ambient temperature with power applied Supply voltage on VDD relative to Vss DC input voltage DC voltage applied to tristate Maximum current into any port pin Maximum current into any port pin configured as analog driver Electrostatic discharge voltage Latch-up current
- See package label -40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 -
125 - - - - - - - - -
See package label 72 +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 - 200
C
Hours
C
V V V mA mA V mA Human body model ESD.
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Operating Temperature
Table 13. Operating Temperature
Symbol TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ - - Max +85 +100 Unit Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 50. The user must limit the power consumption to comply with this requirement.
C C
DC Electrical Characteristics
DC Chip-Level Specifications Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 14. DC Chip-Level Specifications
Symbol VDD Supply voltage IDD Supply current Description Min 3.00 - Typ - 5 Max 5.25 8 Unit V mA Notes Conditions are VDD = 5.0 V, TA = 25 C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are VDD = 3.3 V, TA = 25 C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, VDD = 3.3 V, -40 C TA 55 C. Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 C < TA 85 C. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3 V, -40 C TA 55 C. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3 V, 55 C < TA 85 C. Trimmed for appropriate VDD. Trimmed for appropriate VDD.
IDD3
Supply current
-
3.3
6.0
mA
ISB ISBH ISBXTL ISBXTLH VREF VREF
Sleep (Mode) current with POR, LVD, sleep timer, and WDT.[10] Sleep (Mode) current with POR, LVD, sleep timer, and WDT at high temperature.[10] Sleep (Mode) current with POR, LVD, sleep timer, WDT, and external crystal.[10] Sleep (Mode) current with POR, LVD, sleep timer, WDT, and external crystal at high temperature.[10] Reference voltage (Bandgap) for Silicon A [11] Reference voltage (Bandgap) for Silicon B [11]
- - - - 1.275 1.280
3 4 4 5 1.300 1.300
6.5 25 7.5 26 1.325 1.320
A A A A V V
Notes 10. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. 11. Refer to the Ordering Information on page 53.
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DC GPIO Specifications Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 15. DC GPIO Specifications
Symbol Description Pull-up resistor RPU Pull-down resistor RPD High output level VOH Min 4 4 VDD - 1.0 Typ 5.6 5.6 - Max 8 8 - Unit k k V Notes
VOL
Low output level
-
-
0.75
V
IOH IOL VIL VIH VH IIL CIN COUT
High-level source current Low-level sink current Input low level Input high level Input hysterisis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output
10 25 - 2.1 - - - -
- - - - 60 1 3.5 3.5
- - 0.8 - - 10 10
mA mA V V mV nA pF pF
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOH = VDD - 1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 3.0 to 5.25 VDD = 3.0 to 5.25 Gross tested to 1 A. Package and pin dependent. Temp = 25 C. Package and pin dependent. Temp = 25 C.
DC Operational Amplifier Specifications Table 16 and Table 17 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. The operational amplifier is a component of both the analog continuous time PSoC blocks and the analog switched cap PSoC blocks. The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters apply to 5 V at 25 C and are for design guidance only. Table 16. 5-V DC Operational Amplifier Specifications
Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range Min - - - - - - - - - 0 Typ 1.6 1.6 1.6 1.6 1.6 1.6 4 20 4.5 - Max 10 10 10 10 10 10 20 - 9.5 VDD Units mV mV mV mV mV mV V/C pA pF V Gross tested to 1 A. Package and pin dependent. Temp = 25 C The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes
TCVOSOA IEBOA CINOA VCMOA
Common mode voltage range (high power or high Opamp bias)
0.5
-
VDD - 0.5
V
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Table 16. 5-V DC Operational Amplifier Specifications
Symbol CMRROA Description Common mode rejection ratio Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Open loop gain Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Min 60 60 60 60 60 80 VDD - 0.2 VDD - 0.2 VDD - 0.5 - - - - - - - - - 60 Typ - - - - - - - - - - - - 150 300 600 1200 2400 4600 - Max - - - - - - - - - 0.2 0.2 0.5 200 400 800 1600 3200 6400 - Units dB dB dB dB dB dB V V V V V V A A A A A A dB Vss VIN (VDD - 2.25) or (VDD - 1.25 V) VIN VDD. Notes Specification is applicable at both High and Low opamp bias. Specification is applicable at High opamp bias. For Low opamp bias mode, minimum is 60 dB.
GOLOA
VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high VOLOWOA Low output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Supply voltage rejection ratio
ISOA
PSRROA
Table 17. 3.3-V DC Operational Amplifier Specifications
Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range Min - - - - - - - - - 0.2 Typ 1.4 1.4 1.4 1.4 1.4 - 7 20 4.5 - Max 10 10 10 10 10 - 40 - 9.5 VDD - 0.2 Unit mV mV mV mV mV mV V/C pA pF V Gross tested to 1A. Package and pin dependent. Temp = 25 C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at Low opamp bias. For High bias mode (except High Power, High opamp bias), minimum is 60 dB. Specification is applicable at Low opamp bias. For High opamp bias mode (except High Power, High opamp bias), minimum is 60 dB. Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation.
TCVOSOA IEBOA CINOA VCMOA
CMRROA
Common mode rejection ratio Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low Open loop gain Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low
50 50 50 60 60 80
- - - - - -
- - - - - -
dB dB dB dB dB dB
GOLOA
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Table 17. 3.3-V DC Operational Amplifier Specifications (continued)
Symbol VOHIGHOA Description Min Typ - - - - - - 150 300 600 1200 2400 - 80 Max - - - 0.2 0.2 0.2 200 400 800 1600 3200 - - Unit V V V V V V A A A A A A dB Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. High output voltage swing (internal signals) Power = low, Opamp bias = low VDD - 0.2 VDD - 0.2 Power = medium, Opamp bias = low VDD - 0.2 Power = high, Opamp bias = low Low output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Supply voltage rejection ratio - - - - - - - - - 50
VOLOWOA
ISOA
PSRROA
VSS VIN (VDD - 2.25) or (VDD - 1.25 V) VIN VDD.
DC Low-Power Comparator Specifications Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, 3.0 V to 3.6 V and -40 C TA 85 C, or 2.4 V to 3.0 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V at 25 C and are for design guidance only. Table 18. DC Low-Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC Description Low-power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 - - Typ - 10 2.5 Max VDD - 1 40 30 Unit V A mV
DC Analog Output Buffer Specifications Table 19 and Table 20 on page 24 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 19. 5-V DC Analog Output Buffer Specifications
Symbol VOSOB Description Input offset voltage (absolute value) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Average input offset voltage drift Common-mode input voltage range Output resistance Power = low Power = high High output voltage swing (Load = 32 ohms to VDD/2) Power = low Power = high Low output voltage swing (Load = 32 ohms to VDD/2) Power = low Power = high Min - - - - - 0.5 - - 0.5 x VDD + 1.3 0.5 x VDD + 1.3 - - - Typ 3 3 3 3 5 - 1 1 - - - - - Max 19 19 19 19 30 VDD - 1.0 - - - - - 0.5 x VDD - 1.3 0.5 x VDD - 1.3 Unit mV mV mV mV V/C V V V Notes
TCVOSOB VCMOB ROUTOB VOHIGHOB
VOLOWOB
V V
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Table 19. 5-V DC Analog Output Buffer Specifications (continued)
Symbol ISOB Description Supply current including opamp bias cell (no load) Power = low Power = high Supply voltage rejection ratio Maximum output current Load capacitance Min - - 60 - - Typ 1.1 2.6 64 40 - Max 5.1 8.8 - - 200 Unit mA mA dB mA pF Notes
PSRROB IOMAX CL
This specification applies to the external circuit driven by the analog output buffer.
Table 20. 3.3-V DC Analog Output Buffer Specifications
Symbol VOSOB Description Input offset voltage (absolute value) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Average input offset voltage drift Power = low, Opamp bias = low Power = low, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Common-mode input voltage range Output resistance Power = low Power = high High output voltage swing (load = 32 ohms to VDD/2) Power = low Power = high Low output voltage swing (load = 32 ohms to VDD/2) Power = low Power = high Supply current including opamp bias cell (no load) Power = low Power = high Supply voltage rejection ratio Load capacitance Min - - - - - - - - 0.5 - - 0.5 x VDD + 1.0 0.5 x VDD + 1.0 - - - - 60 - Typ 3.2 3.2 6 6 9 9 12 12 - 1 1 - - - - 0.8 2.0 64 - Max 20 20 25 25 55 55 70 70 VDD - 1.0 - - - - 0.5 x VDD - 1.0 0.5 x VDD - 1.0 2 4.3 - 200 Unit mV mV mV mV V/C V/C V/C V/C V V V V V mA mA dB pF Notes High power setting is not recommended.
TCVOSOB
High power setting is not recommended.
VCMOB ROUTOB VOHIGHOB
VOLOWOB
ISOB
PSRROB CL
This specification applies to the external circuit driven by the analog output buffer.
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DC Switch Mode Pump Specifications Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 21. DC Switch Mode Pump (SMP) Specifications
Symbol VPUMP 5 V VPUMP 3 V IPUMP VBAT5 V VBAT3 V VBATSTART VPUMP_Line Description 5 V output voltage 3 V output voltage Available output current VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.8 V, VPUMP = 5.0 V Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump Line regulation (over VBAT range) Min 4.75 3.00 Typ 5.0 3.25 Max 5.25 3.60 Unit V V Notes Configured as in Note 12. Average, neglecting ripple. SMP trip voltage is set to 5.0 V. Configured as in Note 12. Average, neglecting ripple. SMP trip voltage is set to 3.25 V. Configured as in Note 12. SMP trip voltage is set to 3.25 V. SMP trip voltage is set to 5.0 V. Configured as in Note 12. SMP trip voltage is set to 5.0 V. Configured as in Note 12. SMP trip voltage is set to 3.25 V. Configured as in Note 12. Configured as in Note 12. VO is the "VDD Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 25 on page 33. Configured as in Note 12. VO is the "VDD Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 25 on page 33. Configured as in Note 12. Load is 5 mA. Configured as in Note 12. Load is 5 mA. SMP trip voltage is set to 3.25 V.
8 5 1.8 1.0 1.1 -
- - - - - 5
- - 5.0 3.3 - -
mA mA V V V %VO
VPUMP_Load
Load regulation
-
5
-
%VO
VPUMP_Ripple E3 FPUMP DCPUMP
Output voltage ripple (depends on capacitor/load) Efficiency Switching frequency Switching duty cycle
- 35 - -
100 50 1.3 50
- - - -
mVpp % MHz %
Figure 11. Basic Switch Mode Pump Circuit
D1
Vdd
V PUMP C1
L1 V BAT
+
SMP Battery
PSoC TM
Vss
Note 12. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 11.
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DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 22. 5-V DC Analog Reference Specifications
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b000 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap Min VDD/2 + 1.228 VDD/2 - 0.078 VDD/2 - 1.336 VDD/2 + 1.224 VDD/2 - 0.056 VDD/2 - 1.338 VDD/2 + 1.226 VDD/2 - 0.057 VDD/2 - 1.337 VDD/2 + 1.226 VDD/2 - 0.047 VDD/2 - 1.338 Typ VDD/2 + 1.290 VDD/2 - 0.007 VDD/2 - 1.295 VDD/2 + 1.293 VDD/2 - 0.005 VDD/2 - 1.298 VDD/2 + 1.293 VDD/2 - 0.006 VDD/2 - 1.298 VDD/2 + 1.294 VDD/2 - 0.004 VDD/2 - 1.299 Max VDD/2 + 1.352 VDD/2 + 0.063 VDD/2 - 1.250 VDD/2 + 1.356 VDD/2 + 0.043 VDD/2 - 1.255 VDD/2 + 1.356 VDD/2 + 0.044 VDD/2 - 1.256 VDD/2 + 1.359 VDD/2 + 0.035 VDD/2 - 1.258 Unit V V V V V V V V V V V V
Note 13. AGND tolerance includes the offsets of the local buffer in the PSoC block.
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Table 22. 5-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI Reference Ref High Description P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS Min P2[4] + P2[6] - 0.085 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.077 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.070 P2[4] P2[4] - P2[6] - 0.022 P2[4] + P2[6] - 0.070 P2[4] P2[4] - P2[6] - 0.022 VDD - 0.037 VDD/2 - 0.061 VSS VDD - 0.039 VDD/2 - 0.049 VSS VDD - 0.037 VDD/2 - 0.054 VSS VDD - 0.042 VDD/2 - 0.046 VSS Typ Max Unit V
P2[4] + P2[6] - P2[4] + P2[6] + 0.016 0.044 P2[4] P2[4]
VAGND VREFLO
AGND Ref Low
- V
P2[4] - P2[6] + P2[4] - P2[6] + 0.010 0.055 P2[4] + P2[6] - P2[4] + P2[6] + 0.010 0.051 P2[4] P2[4]
RefPower = high Opamp bias = low
VREFHI
Ref High
V
VAGND VREFLO 0b001
AGND Ref Low
- V
P2[4] - P2[6] + P2[4] - P2[6] + 0.005 0.039 P2[4] + P2[6] - P2[4] + P2[6] + 0.010 0.050 P2[4] P2[4]
RefPower = medium Opamp bias = high
VREFHI
Ref High
V
VAGND VREFLO
AGND Ref Low
- V
P2[4] - P2[6] + P2[4] - P2[6] + 0.005 0.039 P2[4] + P2[6] - P2[4] + P2[6] + 0.007 0.054 P2[4] P2[4]
RefPower = medium Opamp bias = low
VREFHI
Ref High
V
VAGND VREFLO
AGND Ref Low
- V
P2[4] - P2[6] + P2[4] - P2[6] + 0.002 0.032 VDD - 0.009 VDD/2 - 0.006 VSS + 0.007 VDD - 0.006 VDD/2 - 0.005 VSS + 0.005 VDD - 0.007 VDD/2 - 0.005 VSS + 0.006 VDD - 0.005 VDD/2 - 0.004 VSS + 0.004 VDD VDD/2 + 0.047 VSS + 0.028 VDD VDD/2 + 0.036 VSS + 0.019 VDD VDD/2 + 0.041 VSS + 0.024 VDD VDD/2 + 0.034 VSS + 0.017
RefPower = high Opamp bias = high
VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO
Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low
V V V V V V V V V V V V
RefPower = high Opamp bias = low 0b010
RefPower = medium Opamp bias = high
RefPower = medium Opamp bias = low
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Table 22. 5-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b011 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO 0b100 RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 3 x Bandgap 2 x Bandgap Bandgap 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) 2 x Bandgap + P2[6] (P2[6] = 1.3 V) 2 x Bandgap 2 x Bandgap - P2[6] (P2[6] = 1.3 V) Min 3.788 2.500 1.257 3.792 2.518 1.256 3.795 2.516 1.256 3.792 2.522 1.255 2.495 - P2[6] 2.502 2.531 - P2[6] 2.500 - P2[6] 2.519 2.530 - P2[6] 2.503 - P2[6] 2.517 2.529 - P2[6] 2.505 - P2[6] 2.525 2.528 - P2[6] Typ 3.891 2.604 1.306 3.893 2.602 1.302 3.894 2.603 1.303 3.895 2.602 1.301 2.586 - P2[6] 2.604 2.611 - P2[6] 2.591 - P2[6] 2.602 2.605 - P2[6] 2.592 - P2[6] 2.603 2.606 - P2[6] 2.594 - P2[6] 2.602 2.603 - P2[6] Max 3.986 3.699 1.359 3.982 2.692 1.354 3.993 2.698 1.353 3.986 2.685 1.350 2.657 - P2[6] 2.719 2.681 - P2[6] 2.662 - P2[6] 2.693 2.666 - P2[6] 2.662 - P2[6] 2.698 2.665 - P2[6] 2.665 - P2[6] 2.685 2.661 - P2[6] Unit V V V V V V V V V V V V V V V V V V V V V V V V
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Table 22. 5-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO 0b101 RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b110 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b111 VREFHI VAGND VREFLO RefPower = medium Opamp bias = high VREFHI VAGND VREFLO RefPower = medium Opamp bias = low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 2 x Bandgap Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS 3.2 x Bandgap 1.6 x Bandgap VSS Min P2[4] + 1.222 P2[4] P2[4] - 1.331 P2[4] + 1.226 P2[4] P2[4] - 1.331 P2[4] + 1.227 P2[4] P2[4] - 1.331 P2[4] + 1.228 P2[4] P2[4] - 1.332 2.535 1.227 VSS 2.530 1.244 VSS 2.532 1.239 VSS 2.528 1.249 VSS 4.041 1.998 VSS 4.047 2.012 VSS 4.049 2.008 VSS 4.047 2.016 VSS Typ P2[4] + 1.290 P2[4] P2[4] - 1.295 P2[4] + 1.293 P2[4] P2[4] - 1.298 P2[4] + 1.294 P2[4] P2[4] - 1.298 P2[4] + 1.295 P2[4] P2[4] - 1.299 2.598 1.305 VSS + 0.009 2.598 1.303 VSS + 0.005 2.598 1.304 VSS + 0.006 2.598 1.302 VSS + 0.004 4.155 2.083 VSS + 0.010 4.153 2.082 VSS + 0.006 4.154 2.083 VSS + 0.006 4.154 2.081 VSS + 0.004 Max P2[4] + 1.343 P2[4] P2[4] - 1.254 P2[4] + 1.347 P2[4] P2[4] - 1.259 P2[4] + 1.347 P2[4] P2[4] - 1.259 P2[4] + 1.349 P2[4] P2[4] - 1.260 2.644 1.398 VSS + 0.038 2.643 1.370 VSS + 0.024 2.644 1.380 VSS + 0.026 2.645 1.362 VSS + 0.018 4.234 2.183 VSS + 0.038 4.236 2.157 VSS + 0.024 4.238 2.165 VSS + 0.026 4.238 2.150 VSS + 0.018 Unit V - V V - V V - V V - V V V V V V V V V V V V V V V V V V V V V V V V V
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Table 23. 3.3-V DC Analog Reference Specifications
Reference ARF_CR [5:3] Reference Power Settings Symbol Reference VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low 0b000 RefPower = medium Opamp bias = high VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low VAGND VREFLO 0b001 VREFHI RefPower = medium Opamp bias = high VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap VDD/2 + Bandgap VDD/2 VDD/2 - Bandgap P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4] - P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]-P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]-P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) Min VDD/2 + 1.225 VDD/2 - 0.067 VDD/2 - 1.35 VDD/2 + 1.218 VDD/2 - 0.038 VDD/2 - 1.329 VDD/2 + 1.221 VDD/2 - 0.050 VDD/2 - 1.331 VDD/2 + 1.226 VDD/2 - 0.028 VDD/2 - 1.329 P2[4] + P2[6] - 0.098 P2[4] P2[4] - P2[6] - 0.055 P2[4] + P2[6] - 0.082 P2[4] P2[4] - P2[6] - 0.037 P2[4] + P2[6] - 0.079 P2[4] P2[4] - P2[6] - 0.038 P2[4] + P2[6] - 0.080 P2[4] P2[4] - P2[6] - 0.032 Typ Max Unit V V V V V V V V V V V V V - V V - V V - V V - V
VDD/2 + 1.292 VDD/2 + 1.361 VDD/2 - 0.002 VDD/2 + 0.063 VDD/2 - 1.293 VDD/2 - 1.210 VDD/2 + 1.294 VDD/2 + 1.370 VDD/2 - 0.001 VDD/2 + 0.035 VDD/2 - 1.296 VDD/2 - 1.259 VDD/2 + 1.294 VDD/2 + 1.366 VDD/2 - 0.002 VDD/2 + 0.046 VDD/2 - 1.296 VDD/2 - 1.260 VDD/2 + 1.295 VDD/2 + 1.365 VDD/2 - 0.001 VDD/2 + 0.025 VDD/2 - 1.297 VDD/2 - 1.262 P2[4] + P2[6] - 0.018 P2[4] P2[4] - P2[6] + 0.013 P2[4] + P2[6] - 0.011 P2[4] P2[4] - P2[6] + 0.006 P2[4] + P2[6] - 0.012 P2[4] P2[4] - P2[6] + 0.006 P2[4] + P2[6] - 0.008 P2[4] P2[4] - P2[6] + 0.003 P2[4] + P2[6] + 0.055 P2[4] P2[4] - P2[6] + 0.086 P2[4] + P2[6] + 0.050 P2[4] P2[4] - P2[6] + 0.054 P2[4] + P2[6] + 0.047 P2[4] P2[4] - P2[6] + 0.057 P2[4] + P2[6] + 0.055 P2[4] P2[4] - P2[6] + 0.042
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Table 23. 3.3-V DC Analog Reference Specifications
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol Reference VREFHI VAGND VREFLO VREFHI RefPower = high Opamp bias = low 0b010 RefPower = medium Opamp bias = high VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = medium Opamp bias = low 0b011 0b100 All power settings. Not allowed for 3.3 V All power settings. Not allowed for 3.3 V VAGND VREFLO - - VREFHI RefPower = high Opamp bias = high VAGND VREFLO VREFHI RefPower = high Opamp bias = low VAGND VREFLO 0b101 VREFHI RefPower = medium Opamp bias = high VAGND VREFLO VREFHI RefPower = medium Opamp bias = low VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low - - Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss - - P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] - Bandgap (P2[4] = VDD/2) Description Min VDD - 0.06 VDD/2 - 0.05 Vss VDD - 0.060 VDD/2 - 0.028 Vss VDD - 0.058 VDD/2 - 0.037 Vss VDD - 0.057 VDD/2 - 0.025 Vss - - P2[4] + 1.213 P2[4] P2[4] - 1.333 P2[4] + 1.217 P2[4] P2[4] - 1.320 P2[4] + 1.217 P2[4] P2[4] - 1.322 P2[4] + 1.219 P2[4] P2[4] - 1.324 Typ VDD - 0.010 Max VDD Unit V V V V V V V V V V V V - - V V V V V V V V V V V V
VDD/2 - 0.002 VDD/2 + 0.040 Vss + 0.009 VDD - 0.006 Vss + 0.056 VDD
VDD/2 - 0.001 VDD/2 + 0.025 Vss + 0.005 VDD - 0.008 Vss + 0.034 VDD
VDD/2 - 0.002 VDD/2 + 0.033 Vss + 0.007 VDD - 0.006 Vss + 0.046 VDD
VDD/2 - 0.001 VDD/2 + 0.022 Vss + 0.004 - - P2[4] + 1.291 P2[4] P2[4] - 1.294 P2[4] + 1.294 P2[4] P2[4] - 1.296 P2[4] + 1.294 P2[4] P2[4] - 1.297 P2[4] + 1.295 P2[4] P2[4] - 1.297 Vss + 0.030 - - P2[4] + 1.367 P2[4] P2[4] - 1.208 P2[4] + 1.368 P2[4] P2[4] - 1.261 P2[4] + 1.369 P2[4] P2[4] - 1.262 P2[4] + 1.37 P2[4] P2[4] - 1.262
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Table 23. 3.3-V DC Analog Reference Specifications
Reference ARF_CR [5:3] Reference Power Settings RefPower = high Opamp bias = high Symbol Reference VREFHI VAGND VREFLO RefPower = high Opamp bias = low 0b110 RefPower = medium Opamp bias = high VREFHI VAGND VREFLO VREFHI VAGND VREFLO RefPower = medium Opamp bias = low 0b111 All power settings. Not allowed for 3.3 V VREFHI VAGND VREFLO - Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low - Description 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss 2 x Bandgap Bandgap Vss - Min 2.507 1.203 Vss 2.516 1.241 Vss 2.510 1.240 Vss 2.515 1.258 Vss - Typ 2.598 1.307 Vss + 0.012 2.598 1.303 Vss + 0.007 2.599 1.305 Vss + 0.008 2.598 1.302 Vss + 0.005 - Max 2.698 1.424 Vss + 0.067 2.683 1.376 Vss + 0.040 2.693 1.374 Vss + 0.048 2.683 1.355 Vss + 0.03 - Unit V V V V V V V V V V V V -
DC Analog PSoC Block Specifications Table 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 24. DC Analog PSoC Block Specifications
Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switch cap) Min - - Typ 12.2 80 Max - - Unit k fF
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DC POR and LVD Specifications Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 25. DC POR and LVD Specifications
Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description VDD value for PPOR trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for PPOR trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b VDD value for PUMP trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min - - - - - - - - - 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 Max - - - - - - - - - 2.98[14] 3.08 3.20 4.08 4.57 4.74[15] 4.82 4.91 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Unit V V V V V V mV mV mV V V V V V V V V V V V V V V V V Notes VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from watchdog.
Notes 14. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 15. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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DC Programming Specifications Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 26. DC Programming Specifications
Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Unit V Notes This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to this device when it is executing internal flash writes.
VDDLV
Low VDD for verify
3
3.1
3.2
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operation
3
5.25
V
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[17] Flash data retention
- - 2.2 - - - VDD - 1.0 50,000[16] 1,800,000 10
5 - - - - - - - - -
25 0.8 - 0.2 1.5 Vss + 0.75 VDD - - -
mA V V mA mA V V Cycles Cycles Years
Driving internal pull-down resistor. Driving internal pull-down resistor.
Erase/write cycles per block. Erase/write cycles.
DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 27. DC I2C Specifications
Parameter VILI2C[18] VIHI2C[18] Input low level Input high level Description Min - - 0.7 x VDD Typ - - - Max 0.3 x VDD 0.25 x VDD - Units V V V Notes 3.0 V VDD 3.6 V 4.75 V VDD 5.25 V 3.0 V VDD 5.25 V
Notes 16. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 17. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36 x 2 blocks of 25,000 maximum cycles each, or 36 x 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 x 50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids - Reading and Writing PSoC(R) Flash - AN2015 for more information. 18. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the above specs.
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AC Electrical Characteristics
AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 28. AC Chip-Level Specifications
Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 F32K_U Description Internal main oscillator (IMO) frequency CPU frequency (5 V nominal) CPU frequency (3.3 V nominal) Digital PSoC block frequency Digital PSoC block frequency Internal low speed oscillator (ILO) frequency External crystal oscillator ILO untrimmed frequency Min 23.4 0.0914 0.0914 0 0 15 - 5 Typ 24 24 12 48 24 32 32.768 - Max 24.6[19] 24.6[19] 12.3[20] 49.2[19, 21] 24.6[21] 64 - 100 Unit MHz MHz MHz MHz MHz kHz kHz kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this Multiple (x732) of crystal frequency. Notes Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. SLIMO mode = 0. Trimmed. Utilizing factory trim values. SLIMO mode = 0. Refer to AC Digital Block Specifications on page 40.
FPLL tPLLSLEW tPLLSLEWSLOW tOS tOSACC
PLL frequency PLL lock time PLL lock time for low gain setting External crystal oscillator startup to 1% External crystal oscillator startup to 100 ppm
- 0.5 0.5 - -
23.986 - - 1700 2800
- 10 50 2620 3800
MHz ms ms ms ms
The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 W maximum drive level 32.768 kHz crystal. 3.0 V VDD 5.5 V, -40 C TA 85 C.
tXRST DC24M DCILO Step24M tPOWERUP Fout48M FMAX SRPOWER_UP
External reset pulse width 24 MHz duty cycle ILO duty cycle 24 MHz trim step size Time from end of POR to CPU executing code 48 MHz output frequency Maximum frequency of signal on row input or row output. Power supply slew rate
10 40 20 - - 46.8 - -
- 50 50 50 16 48.0 - -
- 60 80 - 100 49.2[19, 20] 12.3 250
s % % kHz ms MHz MHz V/ms VDD slew rate during power-up. wer-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. Trimmed. Utilizing factory trim values.
Notes 19. 4.75 V < VDD < 5.25 V. 20. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC(R) Trims for 3.3 V and 2.7 V Operation - AN2012 for information on trimming for operation at 3.3 V. 21. See the individual user module datasheets for information on maximum frequencies for user modules.
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Table 28. AC Chip-Level Specifications (continued)
Symbol tjit_IMO[22] Description 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) tjit_PLL
[22]
Min - - - - - -
Typ 200 300 100 200 300 100
Max 700 900 400 800 1200 700
Unit ps N = 32
Notes
24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS)
ps
N = 32
Figure 12. PLL Lock Timing Diagram
PLL Enable
TPLLSLEW 24 MHz
FPLL PLL Gain
0
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
PLL Enable
TPLLSLEWLOW 24 MHz
FPLL PLL Gain
1
Figure 14. External Crystal Oscillator Startup Timing Diagram
32K Select
TOS 32 kHz
F32K2
Note 22. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information.
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AC GPIO Specifications Table 29 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 29. AC GPIO Specifications
Symbol FGPIO tRiseF tFallF tRiseS tFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12 18 18 - - Unit MHz ns ns ns ns Notes Normal strong mode VDD = 4.5 to 5.25 V, 10% to 90% VDD = 4.5 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90%
Figure 15. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V. Table 30. 5-V AC Operational Amplifier Specifications
Symbol tROA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Rising slew rate (20% to 80%)(10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling slew rate (20% to 80%)(10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Min - - - - - - 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 - Typ - - - - - - - - - - - - - - - 100 Max 3.9 0.72 0.62 5.9 0.92 0.72 - - - - - - - - - - Unit s s s s s s V/s V/s V/s V/s V/s V/s MHz MHz MHz nV/rt-Hz
tSOA
SRROA
SRFOA
BWOA
ENOA
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Table 31. 3.3-V AC Operational Amplifier Specifications
Symbol tROA tSOA SRROA SRFOA BWOA ENOA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = low, Opamp bias = low Power = low, Opamp bias = high Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Rising slew rate (20% to 80%)(10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling slew rate (20% to 80%)(10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Min - - - - 0.31 2.7 0.24 1.8 0.67 2.8 - Typ - - - - - - - - - - 100 Max 3.92 0.72 5.41 0.72 - - - - - - - Units s s s s V/s V/s V/s V/s MHz MHz nV/rt-Hz
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor. Figure 16. Typical AGND Noise with P2[4] Bypass
nV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
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At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 17. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low-Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, 3.0 V to 3.6 V and -40 C TA 85 C, or 2.4 V to 3.0 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V at 25 C and are for design guidance only. Table 32. AC Low-Power Comparator Specifications
Symbol tRLPC Description LPC response time Min - Typ - Max 50 Unit s Notes 50 mV overdrive comparator reference set within VREFLPC.
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AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 33. AC Digital Block Specifications
Function All functions Description Block input clock frequency VDD 4.75 V VDD < 4.75 V Timer Input clock frequency No capture, VDD 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Dead Band Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD 4.75 V VDD < 4.75 V CRCPRS (PRS Mode) Input clock frequency VDD 4.75 V VDD < 4.75 V CRCPRS (CRC Mode) SPIM SPIS Input clock frequency Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions Transmitter Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Receiver Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V - - - - - - 49.2 24.6 24.6 MHz MHz MHz - - - - - - 49.2 24.6 24.6 MHz MHz MHz The baud rate is equal to the input clock frequency divided by 8. - - - - - 50
[23]
Min - - - - - 50[23] - - - 50[23] 20 50[23] 50[23] - -
Typ - - - - - - - - - - - - - - - - - - - - -
Max 49.2 24.6 49.2 24.6 24.6 - 49.2 24.6 24.6 - - - - 49.2 24.6 49.2 24.6 24.6 8.2 4.1 -
Unit MHz MHz MHz MHz MHz ns MHz MHz MHz ns ns ns ns MHz MHz MHz MHz MHz MHz MHz ns
Notes
The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode.
The baud rate is equal to the input clock frequency divided by 8.
Note 23. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 34. 5-V AC Analog Output Buffer Specifications
Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1 V Step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1 V Step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 Typ - - - - - - - - - - - - Max 2.5 2.5 2.2 2.2 - - - - - - - - Unit s s s s V/s V/s V/s V/s MHz MHz kHz kHz
Table 35. 3.3-V AC Analog Output Buffer Specifications
Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1 V Step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1 V Step, 100 pF load Power = low Power = high Small signal bandwidth, 20m Vpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min - - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200 Typ - - - - - - - - - - - - Max 3.8 3.8 2.6 2.6 - - - - - - - - Unit s s s s V/s V/s V/s V/s MHz MHz kHz kHz
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AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 36. 5-V AC External Clock Specifications
Symbol FOSCEXT - - - Frequency High period Low period Power-up IMO to switch Description Min 0.093 20.6 20.6 150 Typ - - - - Max 24.6 5300 - - Unit MHz ns ns s
Table 37. 3.3-V AC External Clock Specifications
Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU clock divide by 1[24] Frequency with CPU clock divide by 2 or greater[25] High period with CPU clock divide by 1 Low period with CPU clock divide by 1 Power-up IMO to switch Min 0.093 0.186 41.7 41.7 150 Typ - - - - - Max 12.3 24.6 5300 - - Unit MHz MHz ns ns s
AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40 C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 38. AC Programming Specifications
Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tERASEALL tPROGRAM_HOT tPROGRAM_COLD Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (Block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (Bulk) Flash block erase + flash block write time Flash block erase + flash block write time Min 1 1 40 40 0 - - - - - - - Typ - - - - - 30 10 - - 95 - - Max 20 20 - - 8 - - 45 50 - 80[26] 160[26] Unit ns ns ns ns MHz ms ms ns ns ms ms ms Notes
VDD 3.6 3.0 VDD 3.6 Erase all Blocks and protection fields at once 0 C Tj 100 C -40 C Tj 0 C
Notes 24. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 25. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 26. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids - Reading and Writing PSoC(R) Flash - AN2015 for more information.
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AC I2C Specifications Table 39 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40C TA 85 C, or 3.0 V to 3.6 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 39. AC Characteristics of the I2C SDA and SCL Pins
Symbol FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated. Low period of the SCL clock High period of the SCL clock Set up time for a repeated start condition Data hold time Data set up time Set up time for stop condition Bus-free time between a stop and start condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - Fast Mode Min Max 0 400 0.6 - 1.3 0.6 0.6 0 100[27] 0.6 1.3 0 - - - - - - - 50 Unit kHz s s s s s ns s s ns
Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C THDDATI2CTSUSTAI2C TSPI2C
TBUFI2C
P
S
STOP Condition
Note 27. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Packaging Information
This section illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 19. 8-pin (300-Mil) PDIP
0.380 0.390
4 1
PIN 1 ID
DIMENSIONS IN INCHES MIN.
0.240 0.260
MAX.
5
8
0.100 BSC. SEATING PLANE
0.300 0.325
0.180 MAX.
0.115 0.145
0.125 0.140
0.015 MIN.
0.008 0.015
0-10
0.055 0.070 0.014 0.022
0.430 MAX.
51-85075 *B
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Figure 20. 20-pin (210-Mil) SSOP
51-85077 *D
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Figure 21. 20-pin (300-Mil) Molded SOIC
51-85024 *E
Figure 22. 28-pin (300-Mil) Molded DIP
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES[MM]
0.260[6.60] 0.295[7.49]
MIN. MAX.
REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15gms PART #
15
28
0.030[0.76] 0.080[2.03]
P28.3 PZ28.3
SEATING PLANE
STANDARD PKG. LEAD FREE PKG.
1.345[34.16] 1.385[35.18]
0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 3 MIN.
0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50]
0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79]
0.310[7.87] 0.385[9.78] SEE LEAD END OPTION
LEAD END OPTION (LEAD #1, 14, 15 & 28)
51-85014 *E
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Figure 23. 28-pin (210-Mil) SSOP
51-85079 *D
Figure 24. 28-pin (300-Mil) Molded SOIC
51-85026 *F
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Figure 25. 44-pin TQFP
51-85064 *E
Figure 26. 48-pin (300-Mil) SSOP
.020
24 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620 0.630
0.088 0.092
0.095 0.110
SEATING PLANE GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.004
0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85061 *D
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Figure 27. 48-pin QFN 7 x 7 x 0.90 mm (Sawn Type)
TOP VIEW SIDE VIEW
7.000.100
0.9000.100
BOTTOM VIEW
48 1 PIN 1 DOT LASER MARK
37 36
0.200 REF.
0.25 +0.05 -0.07
5.100 REF
0.50 PITCH 37 36 PIN1 ID R 0.20 1 0.45
7.000.100
5.100 REF
SOLDERABLE EXPOSED PAD
25 12 24 13
5.5000.100
12 13 24
25
0.020 +0.025 -0.00
0.400.10
SEATING PLANE
C
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MILLIMETERS
0.08
5.5000.100
001-13191 *E
Figure 28. 56-pin (300-Mil) SSOP
51-85062 *D
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note, Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
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Thermal Impedances
Table 40. Thermal Impedances per Package
Package 8-pin PDIP 20-pin SSOP 20-pin SOIC 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN[29] 56-pin SSOP Typical JA[28] 8-pin PDIP 20-pin SSOP 20-pin SOIC 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN 56-pin SSOP 120 C/W 116 C/W 79 C/W 67 C/W 95 C/W 68 C/W 61 C/W 69 C/W 18 C/W 47 C/W
Capacitance on Crystal Pins
Table 41. Typical Package Capacitance on Crystal Pins
Package Package Capacitance 2.8 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.6 pF 3.3 pF 2.3 pF 3.3 pF
Solder Reflow Peak Temperature
The following table lists the maximum solder reflow peak temperature to achieve good solderability. Thermap ramp rate should 3 or lower.
Table 42. Solder Reflow Peak Temperature
Package 8-pin PDIP 20-pin SSOP 20-pin SOIC 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN 56-pin SSOP Maximum Peak Temperature[30] 260 C 260 C 260 C 260 C 260 C 260 C 260 C 260 C 260 C 260 C Time at Maximum Temperature[31] 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s
C
Notes 28. TJ = TA + POWER x JA. 29. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
30.Refer to Table 44 on page 53. 31. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5 oC with Sn-Pb or 245 5 oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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Development Tool Selection
This chapter presents the development tools available for all current PSoC device families including the CY8C27x43 family.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store.
CY3210-MiniProg1
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler.
PSoC Programmer
The CY3210-MiniProg1 kit lets you to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-pin CY8C29466-24PXI PDIP PSoC Device Sample 28-pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online Store.
CY3215-DK Basic Development Kit
CY3210-PSoCEval1
The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface lets you to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

Evaluation Board with LCD Module MiniProg Programming Unit 28-pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240 V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack
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Device Programmers
All device programmers can be purchased from the Cypress Online Store.
CY3216 Modular Programmer CY3207ISSP In-System Serial Programmer (ISSP)
The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240 V Power Supply, Euro-Plug Adapter USB 2.0 Cable
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Accessories (Emulation and Programming)
Table 43. Emulation and Programming Accessories
Part # CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24SXI CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24SXI CY8C27543-24AXI CY8C27643-24PVXI CY8C27643-24LKXI CY8C27643-24LTXI Pin Package 8-pin PDIP 20-pin SSOP 20-pin SOIC 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN 48-pin QFN Flex-Pod Kit[32] CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXXQFN CY3250-27XXXQFN Foot Kit[33] CY3250-8PDIP-FK CY3250-20SSOP-FK CY3250-20SOIC-FK CY3250-28PDIP-FK CY3250-28SSOP-FK CY3250-28SOIC-FK CY3250-44TQFP-FK CY3250-48SSOP-FK CY3250-48QFN-FK CY3250-48QFN-FK Adapter[34] Adapters can be found at http://www.emulation.com.
Notes 32. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 33. Foot kit includes surface mount feet that can be soldered to the target PCB. 34. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
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Ordering Information
The following table lists the CY8C27x43 PSoC device's key package features and ordering codes.
Table 44. CY8C27x43 PSoC Device Key Features and Ordering Information
Analog Blocks (Columns of 3) Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range Digital I/O Pins XRES Pin No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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Ordering Code
Package
8-pin (300-Mil) DIP 20-pin (210-Mil) SSOP 20-pin (210-Mil) SSOP (Tape and Reel) 20-pin (300-Mil) SOIC 20-pin (300-Mil) SOIC (Tape and Reel) 28-pin (300-Mil) DIP 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (Tape and Reel) 28-pin (300-Mil) SOIC 28-pin (300-Mil) SOIC (Tape and Reel) 44-pin TQFP 44-pin TQFP (Tape and Reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (Tape and Reel)
CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24PVXIT CY8C27243-24SXI CY8C27243-24SXIT CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24PVXIT CY8C27443-24SXI CY8C27443-24SXIT CY8C27543-24AXI CY8C27543-24AXIT CY8C27643-24PVXI CY8C27643-24PVXIT
16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K
256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256 256
No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
-40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
6 16 16 16 16 24 24 24 24 24 40 40 44 44 44 44 44
4 8 8 8 8 12 12 12 12 12 12 12 12 12 12 12 14
48-pin (7 x 7 x 0.90 mm) QFN CY8C27643-24LTXI (Sawn) 48-pin (7 x 7 x 0.90 mm) QFN CY8C27643-24LTXIT (Sawn) 56-pin OCD SSOP
CY8C27002-24PVXI[35] 16 K
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Note 35. This part may be used for in-circuit debugging. It is NOT available for production.
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Analog Outputs 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Flash (Bytes)
RAM (Bytes)
Analog Inputs
CY8C27143, CY8C27243 CY8C27443, CY8C27543 CY8C27643
Ordering Code Definitions
CY 8 C 27 xxx-24xx
Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LKX/LTX /LQX/LCX= QFN Pb-free AX = TQFP Pb-free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended
Document Number: 38-12012 Rev. *T
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Acronyms
Table 45 lists the acronyms that are used in this document.
Table 45. Acronyms Used in this Datasheet
Acronym Description Acronym Description
AC ADC API CMOS CPU CRC CT DAC DC DTMF ECO EEPROM GPIO ICE IDE ILO IMO I/O IrDA ISSP LCD LED LPC LVD MAC MCU
alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator electrically erasable programmable read-only memory general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output infrared data association in-system serial programming liquid crystal display light-emitting diode low power comparator low voltage detect multiply-accumulate microcontroller unit
MIPS OCD PCB PDIP PGA PLL POR PPOR PRS PSoC PWM QFN RTC SAR SC SMP SOIC SPI SRAM SROM SSOP TQFP UART USB WDT XRES
million instructions per second on-chip debug printed circuit board plastic dual-in-line package programmable gain amplifier phase-locked loop power on reset precision power on reset pseudo-random sequence Programmable System-on-Chip pulse width modulator quad flat no leads real time clock successive approximation switched capacitor switch mode pump small-outline integrated circuit serial peripheral interface static random access memory supervisory read only memory shrink small-outline package thin quad flat pack universal asynchronous reciever / transmitter universal serial bus watchdog timer external reset
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC(R) Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids - Reading and Writing PSoC(R) Flash - AN2015 (001-40459) Adjusting PSoC(R) Trims for 3.3 V and 2.7 V Operation - AN2012 (001-17397) Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages - available at http://www.amkor.com.
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Document Conventions
Units of Measure
Table 46 lists the unit sof measures.
Table 46. Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
dB C fF pF kHz MHz rt-Hz k A mA nA pA s
decibels degree Celsius femto farad picofarad kilohertz megahertz root hertz kilohm ohm microampere milliampere nanoampere pikoampere microsecond
ms ns ps V mV mVpp nV V W W mm ppm %
millisecond nanosecond picosecond microvolts millivolts millivolts peak-to-peak nanovolts volts microwatts watt millimeter parts per million percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
Glossary
active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum.
analog blocks
analog-to-digital (ADC) Application programming interface (API) asynchronous Bandgap reference bandwidth
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Glossary (continued)
bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to `1'.
block
buffer
bus
clock
comparator
compiler configuration space crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation.
debugger
dead band digital blocks
digital-to-analog (DAC)
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Glossary (continued)
duty cycle emulator The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer).
External Reset (XRES) Flash
Flash block
frequency gain I2C
ICE
input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
interrupt service routine (ISR)
jitter
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device.
master device
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Glossary (continued)
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. Cypress Semiconductor's PSoC(R) is a registered trademark and Programmable System-on-ChipTM is a trademark of Cypress.
mixed-signal modulator noise
oscillator parity
Phase-locked loop (PLL) pinouts
port Power on reset (POR) PSoC(R)
PSoC DesignerTM The software for Cypress' Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
register reset ROM
serial
settling time
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Glossary (continued)
shift register slave device A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
SRAM
SROM
stop bit synchronous
tri-state
UART user modules
user space
VDD VSS watchdog timer
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Document History Page
Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643, PSoC(R) Programmable System-on-ChipTM Document Number: 38-12012 Origin of Submission Revision ECN Description of Change Change Date ** 127087 New Silicon. 7/01/2003 New document (Revision **). *A 128780 Engineering and 7/29/2003 New electrical spec additions, fix of Core Architecture links, corrections to NWJ some text, tables, drawings, and format. *B 128992 NWJ 8/14/2003 Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter. *C 129283 NWJ 8/28/2003 Significant changes to the Electrical Specifications section. *D 129442 NWJ 9/09/2003 Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts. *E 130129 NWJ 10/13/2003 Revised document for Silicon Revision A. *F 130651 NWJ 10/28/2003 Refinements to Electrical Specification section and I2C chapter. *G 131298 NWJ 11/18/2003 Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscellaneous register changes. *H 229416 SFV See ECN New datasheet format and organization. Reference the PSoC Programmable System-on-Chip Technical Reference Manual for additional information. Title change. *I 247529 SFV See ECN Added Silicon B information to this datasheet. *J 355555 HMT See ECN Add DS standards, update device table, swap 48-pin SSOP 45 and 46, add Reflow Peak Temp. table. Add new color and logo. Re-add pinout ISSP notation. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. *K 523233 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table. Add OCD pinout and package diagram. Add ISSP note to pinout tables. Update package diagram revisions. Update typical and recommended Storage Temperature per industrial specs. Update CY branding and QFN convention. Update copyright and trademarks. *L 2545030 YARA 07/29/2008 Added note to DC Analog Reference Specification table and Ordering Information. *M 2696188 DPT/PYRS 04/22/2009 Changed title from " CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final datasheet" to "CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC(R) Programmable System-on-ChipTM". Updated datasheet template. Added 48-Pin QFN (Sawn) package outline diagram and Ordering information details for CY8C27643-24LTXI and CY8C27643-24LTXIT parts *N 2762501 MAXK 09/11/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Modified TWRITE specification. Replaced TRAMP (time) specification with SRPOWER_UP (slew rate) specification. Added note [9] to Flash Endurance specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. *O 2811860 ECU 11/20/2009 Added Contents page. In the Ordering Information table, added 48 Sawn QFN (LTXI) to the Silicon B parts. Updated 28-Pin package drawing (51-85014)
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Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643, PSoC(R) Programmable System-on-ChipTM Document Number: 38-12012 Origin of Submission Revision ECN Description of Change Change Date *P 2899847 NJF/HMI 03/26/10 Added CY8C27643-24LKXI and CY8C27643-24LTXI to Emulation and Programming Accessories on page 52. Updated Cypress website links. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings on page 19. Updated AC electrical specs. Updated Note in Packaging Information on page 44. Updated package diagrams. Updated Thermal Impedances, Solder Reflow Peak Temperature, and Capacitance on Crystal Pins. Removed Third Party Tools and Build a PSoC Emulator into your Board. Updated Ordering Code Definitions on page 54. Updated Ordering Information table. Updated links in Sales, Solutions, and Legal Information. *Q 2949177 ECU 06/10/2010 Updated content to match current style guide and datasheet template. No technical updates *R 3032514 NJF 09/17/10 Added PSoC Device Characteristics table . Added DC I2C Specifications table. Added F32K_U max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated Analog reference tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 13 since the labelling for y-axis was incorrect. Template and styles update. *S 3092470 GDK 11/22/10 Removed the following pruned parts from the datasheet. CY8C27643-24LFXIT CY8C27643-24LFXI *T 3180303 HMI 02/23/2011 Updated Packaging Information.
Document Number: 38-12012 Rev. *T
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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(c) Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12012 Rev. *T
Revised February 23, 2011
Page 63 of 63
PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) and CapSense(R) are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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